www.siliconstandard.com 1 of 5 n-channel enhancement-mode power mosfet bv dss 650v r ds(on) 0.75w i d 9a the SSM09N70GP-A achieves fast switching performance with low gate charge without a complex drive circuit. it is suitable for high voltage applications such as ac/dc pb-free; rohs - compliant to-220 product summary description notes: 1. pulse width must be limited to avoid exceeding the safe operating area. 2. pulse width <300us, duty cycle <2%. 3. starting tj = 25c, v dd =50v , l=6.8mh , r g =25w, i as = 9a. converters, smps and general off-line switching circuits. the SSM09N70GP-A is in to-220 for through-hole mounting where a small footprint is required on the board, g d s to-2 20 (suffix p) and/or an external heatsink is to be attached. these devices are manufactured with an advanced process, providing improved on-resistance and switching performance. a bsolute maximum ratings symbol parameter value units v ds v gs i d i dm p d w /c e as single p ulse a valanche e nerg y 3 t stg t j symbol parameter value units r q jc maximum t hermal r esistance , ju nction-case 0.8 c/w r q ja maximum thermal resistance, junction-ambient 62 c/w drain- s ource v oltage 650 v gate-source voltage 30 v continuous d rain c urrent, t c = 25c 9 a t c = 100c 5 a pulsed drain current 1 40 a total p ower d issipation , t c = 25c 156 w -55 to 1 5 0 c operating j unction t emperature r ange -55 to 1 5 0 c linear d erating f actor 1.25 305 mj t hermal characteristics storage t emperature r ange SSM09N70GP-A 9 /29/2006 re v.3.1 i ar avalanche current 9 a e ar repetitive avalanche energy 9 mj
electrical characteristics (at tj = 25c, unless otherwise specified) notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d = 1ma 650 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.6 - v/c r ds(on) static drain-source on-resistance v gs =10v, i d =4.5a - - 0.75 w v gs(th) gate threshold voltage v ds =v gs , i d =250ua 2 - 4 v g fs forward transconductance v ds =10v, i d =4.5a - 4.5 - s i dss drain-source leakage current v ds =600v, v gs =0v - - 10 ua v ds =480v ,v gs =0v, t j = 150c - - 100 ua i gss gate-source leakage current v gs =30v - - 100 na q g total gate charge 2 i d =9a - 44 - nc q gs gate-source charge v ds =480v - 11 - nc q gd gate-drain ("miller") charge v gs =10v - 12 - nc t d(on) turn-on delay time 2 v ds =300v - 19 - ns t r rise time i d =9a - 21 - ns t d(off) turn-off delay time r g =10w , v gs =10v - 56 - ns t f fall time r d =34w - 24 - ns c iss input capacitance v gs =0v - 2660 - pf c oss output capacitance v ds =25v - 170 - pf c rss reverse transfer capacitance f=1.0mhz - 10 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward voltage 2 i s = 9a, v gs =0v - - 1.5 v i s continuous source current (body diode) v d =v g =0v , v s =1.5v - - 9 a i sm pulsed source current (body diode) 1 - - 40 a www.siliconstandard.com 2 of 5 SSM09N70GP-A 9 / 2 9 /2006 re v.3.1
www.siliconstandard.com 3 of 5 SSM09N70GP-A 9 / 2 9 /2006 re v.3.1 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. normalized bv dss vs. junction fig 4. normalized on-resistance temperature vs. junction temperature fi g 5. forward characteristic of f fig 6. gate threshold voltage vs. reverse diode junction temperature 0.8 0.9 1 1.1 1.2 -50 0 50 100 150 t j , junction temperature ( o c) normalized bv dss (v) 0 2 4 6 8 10 03691 2 v ds , drain-to-source voltage (v) i d , drain current (a) t c =25 o c 10v 6.0v 5.0v 4.5v 4.0v v g = 3 .5 v 0 1 2 3 -50 0 50 100 150 t j , junction temperature ( o c ) normalized r ds(on) i d =4.5a v g =10v 0 2 4 6 8 10 0 5 10 15 20 25 v ds , drain-to-source voltage (v) i d , drain current (a) t c =150 o c 10v 6.0v 5.0v 4.5v 4.0v v g = 3 .5 v 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j = 150 o c t j = 25 o c 1 2 3 4 5 -50 0 50 100 150 t j , junction temperature ( o c) v gs(th) (v)
www.siliconstandard.com 4 of 5 SSM09N70GP-A 9 / 2 9 /2006 re v.3.1 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 t , pulse width (s) normalized thermal response (r thjc ) p dm duty factor = t/t peak t j = p dm x r thjc + t c t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse 0.1 1 10 100 1 10 100 1000 10000 v ds , drain-to-source voltage (v) i d (a) t c =25 o c single pulse 10us 100us 1ms 10ms 100ms 0 4 8 12 16 02 04 06 0 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =9a v ds =320v v ds =400v v ds =480v 1 100 10000 1 5 9 13 17 21 25 29 v ds , drain-to-source voltage (v) c (pf) f =1.0mh z c iss c oss c rss t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 10v q gs q gd q g charge
www.siliconstandard.com 5 of 5 physical dimensions - to-220 part marking - to-220 packing: moisture sensitivity level msl3 1000pcs in tubes packed inside a 09n70p-a ywwsss date/lot code: y = last digit of the year ww = work week (01 -> 52) sss = lot code sequence part number: 09n70gp-a = SSM09N70GP-A moisture barrier bag (mbb). in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. 1. all dimensions are in m illimeters. 2. dimensions do not include m old protrusions. millimeters min nom max a 4.25 4.48 4.70 b 0.65 0.80 0.90 b1 1.15 1.38 1.60 c 0.40 0.50 0.60 c1 1.00 1.20 1.40 e 9.70 10.00 10.40 e ---- 2.54 ---- l 12.70 13.60 14.50 l1 2.60 2.80 3.00 l2 1.00 1.40 1.80 l3 2.6 3.10 3.6 l4 14.70 15.50 16 l5 6.30 6.50 6.70 f 3.50 3.60 3.70 d 8.40 8.90 9.40 symbols e b b1 e d l3 l4 l1 l2 a c1 c l f l5 SSM09N70GP-A 9 / 2 9 /2006 re v.3.1
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